Detecting the occurrence of desired values on a bus

ABSTRACT

A circuit determining whether a present value transmitted on a bus equals any of several desired values. The circuit may contain a monitor random access memory (RAM) and a monitor circuit. The bits of a desired value at a second set of positions are stored in a location (of the monitor RAM) having an address formed by the bits of the desired value at the a first set of positions. When a value (“present value”) is transmitted on the bus, the bits of the present value at the first set of positions are provided as an address to the monitor RAM, which generates the bits stored in the addressed location as output. The monitor circuit compares the output of monitor RAM with the bits of the present value at the second set of positions to generate a result. The result indicates if the a desired value has occurred on the bus.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to digital processing systems, andmore specifically to a method and apparatus for detecting the occurrenceof desired values on a bus.

[0003] 2. Related Art

[0004] Buses often transfer values between components in digitalprocessing systems (e.g., computers, machine controllers, calculators,etc.). For example, a processor sends an address of an addressable unit(e.g., memory unit or peripheral units) and receives data stored at theaddressed location. Both the address and data are transmitted on a busduring such transactions. The addresses, data, and any digital values ingeneral, are together referred to as values in the subject patentapplication.

[0005] A need often exists to detect the occurrence of desired values ona bus. For example, a programmer may wish to know the execution of aspecific sub-routine contained in a large program, and the access of amemory location corresponding to the entry point of the sub-routine maythus be of interest. Thus, when the address of the memory locationoccurs on a bus storing the program instructions, the programmer candetermine that the sub-routine has been accessed.

[0006] Several approaches have been used in the prior art which enable aprogrammer to detect the occurrence of desired values on a bus. In oneapproach (“first approach”), a set of comparators may be used, with eachcomparator comparing a bit of the value on the bus with a correspondingbit of the desired value to be detected. When all the comparatorsindicate match, the desired value is deemed to have occurred. Oneproblem with such an approach is that a large number of comparators maybe required when many values have to be detected. Accordingly, theapproach may not scale well at least to situations when a large numberof desired values are to be detected.

[0007] An alternative approach (“second approach”) may address some ofthe deficiencies of the first approach if the values to be detected areconsecutive, that is, falling within a range. In such an alternativeapproach, only a subset (typically the more significant bits) of thebits on the bus may be compared. The compared bit positions determine arange as is well known in the relevant arts. If a match is detected, aprogrammer may determine that one of the values in the range hasoccurred on the bus. One problem with the alternative approach is thatit may be desirable to detect the occurrence of specific value (s), andthe approach may not provide such information.

[0008] Another approach (“third approach”) may overcome the notedproblem of the second approach. The third approach may use a page-lookuprandom access memory (RAM) containing the same number of locations asthe number of values possibly represented on a bus, but only with asingle bit in each location. Each bit (memory location) of thepage-lookup table may be set to one logical value to indicate that thecorresponding value needs to be detected, and to another logical valueotherwise.

[0009] Each value on the bus is also provided as an address to thepage-lookup RAM, and the output of the page-lookup RAM indicates whethera desired value has been transmitted on the bus. Thus, using the thirdapproach one may conveniently detect the occurrence of any desiredaddress values (can be random). However, the approach generally requiresthat a page-lookup RAM have the same number of locations as the numberof values possibly represented on the bus, and may not be suitable inenvironments using large bus width. In general, large RAMs consume acorresponding amount of space, and minimizing space consumption isdesirable in many environments.

[0010] Therefore, what is needed is a method and an apparatus whichpotentially minimizes the additional space consumed and can yetefficiently detect the occurrence of any desired values on a bus.

SUMMARY OF THE INVENTION

[0011] A detection circuit provided in accordance with the presentinvention detects the occurrence of one or more desired values on a buswithout requiring a large memory. In one embodiment, the detectioncircuit contains a monitor random access memory (RAM) and a monitorcircuit. The monitor RAM contains multiple locations, with each locationbeing addressed by a corresponding X-bit address.

[0012] Each desired value is associated with a corresponding location(in the monitor RAM) if the bits at a first set of positions matches thecorresponding bits of the X-bit address (of the location). Each locationcontains the bits corresponding to a second set of positions of anassociated desired value.

[0013] The value (“present value”) transmitted on the bus forms theinput to the detection circuit. The bits corresponding to the first setof positions of the present value are provided as an address to themonitor RAM. The monitor RAM provides the data stored at a locationcorresponding to the address as an output.

[0014] Monitor circuit may contain comparators which compare the outputof the monitor RAM with the bits corresponding to the second set ofpositions of the present value to generate a result. The resultindicates whether the present value equals at least one of the desiredvalues.

[0015] Another aspect of the present invention enables multiple desiredvalues to share the same values in the first set of positions. In oneembodiment, multiple monitor RAMs are used, with different desiredvalues sharing the same bits in the first of positions being stored atthe same address in different RAMs.

[0016] Alternatively, each of the memory locations of the monitor RAMcontains multiple cells, with each cell storing the bits at the secondset of position of a corresponding desired value. Thus, each cell maycontain a number of bits equal to the bits in the second set ofpositions.

[0017] The monitor circuit may contain a number of comparators equal tothe number of cells in each monitor RAM location. Each comparatorcompares the content of the corresponding cell with the bitscorresponding to the second set of positions of the present value. As aresult, the output of a comparator indicates whether a desired valueequals the present value received on the bus. In one embodiment, eachRAM location contains four cells and accordingly four comparators may beemployed.

[0018] One more aspect of the present invention enables a flag to beassociated with each cell. The flag is set to one logical value(e.g., 1) if the corresponding cell stores data representing a desiredvalue and to another logical value (0) otherwise. A valid desired valueis said to be present when the flag indicates that the cell containsdata representing a desired value. The comparators may generate a matchonly if the flag of a compared cell indicates that a desired value isrepresented.

[0019] According to one more aspects of the present invention, thenumber of bits in the first set of positions and the number of bits inthe second set of positions equal the total number of bits in thedesired value. In such a situation, the value in each cell (inassociation with the address of the location) represents a correspondingdesired value. However, the bits in the first and second set ofpositions, need not be equal to the total number of bits in the desiredvalue. When such an equality does not exists, the value in each cellrepresents a range of desired values.

[0020] In addition, the first set of positions and the second set ofpositions may be implemented to be in consecutive positions forsimplicity of design. However, alternative embodiments can beimplemented in which the positions are not consecutive. The detectioncircuit may be implemented in several environments such as generalpurpose computer systems and real time embedded systems.

[0021] Further features and advantages of the invention, as well as thestructure and operation of various embodiments of the invention, aredescribed in detail below with reference to the accompanying drawings.In the drawings, like reference numbers generally indicate identical,functionally similar, and/or structurally similar elements. The drawingin which an element first appears is indicated by the leftmost digit(s)in the corresponding reference number.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be described with reference to theaccompanying drawings, wherein:

[0023]FIG. 1 is a block diagram illustrating an example environment inwhich the present invention can be implemented; and

[0024]FIG. 2 is a block diagram illustrating the details of anembodiment of a multiplexer in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] 1. Overview and Discussion of the Invention

[0026] The present invention can be used to determine whether a presentvalue on a bus equals any one of several desired values. A random accessmemory (RAM) may be used to efficiently make such a determination. TheRAM is referred to as a monitor RAM to differentiate from RAMs (“dataRAM”) used for storing data and instructions. The manner in which thedetermination can be made is described below in further detail.

[0027] The values (both present and desired) may logically be viewed asbeing formed by a number of bits at corresponding positions. Thepositions may be partitioned as containing at least two sets, referredto as a first set of positions and a second set of positions. A desiredvalue is associated with a location of the monitor RAM only if the bits(of the desired value) together at the first set of positions equal theaddress of the location. The content of a location of the monitor RAM isset to the bits (of the associated desired value) in the second set ofpositions.

[0028] In operation, when a present value is transmitted on a bus, thebits of the present value corresponding to the first set of positionsare provided as an address to the monitor RAM. The content of theaccessed location are compared with the bits corresponding to the secondset of positions of the present value. The present value is deemed toequal the desired value associated with the accessed monitor RAMlocation.

[0029] Several aspects of the invention are described below withreference to example environments for illustration. It should beunderstood that numerous specific details, relationships, and methodsare set forth to provide a full understanding of the invention. Oneskilled in the relevant art, however, will readily recognize that theinvention can be practiced without one or more of the specific details,or with other methods, etc. In other instances, well-known structures oroperations are not shown in detail to avoid obscuring the invention.

[0030] 2. Example Environment

[0031]FIG. 1 is a block diagram illustrating an example environment inwhich the present invention can be implemented. There is shown system100 containing processor 110, monitor RAM 120, monitor circuit 130,trace block 140, data RAMs (random access memories) 150-160, interface190 and peripheral devices 170-180. Each component is described infurther detail below.

[0032] Processor 110 accesses the data values stored in data RAMs150-160 by sending an address on bus 155. Thus, bus 155 generallycarries addresses sent by processor 110 and the data values transmittedin response. The data (address and data values) transmitted on bus 155is referred to as a present value. The present invention can be used todetermine whether the present value equals any one of a desired set ofvalues.

[0033] In one embodiment, a general purpose computer system representssystem 100, and processor 110 is referred to as a central processingunit (CPU). Alternatively, system 100 may represent special purposeprocessing systems such as those used in real-time embedded systems. Ingeneral, system 100 may be implemented in different types ofenvironments. Processor 110 and data RAMs 150 and 160 may be implementedin a known way.

[0034] Peripheral devices 170 and 180 are used for input or outputoperations. For example, in a computer system, keyboards, printers,etc., are examples peripheral devices. Interface 190 may be used tocontrol one or more external systems. The need to control externalsystems typically exists in real-time environments (e.g., an externalmotor being controlled by system 100). Peripheral devices 170 and 180,and data RAMs 150 and 160 are examples of addressable units and arereferred to as such because data available from the units can beaccessed by sending a corresponding address.

[0035] Trace system 140 receives signals indicating whether a presentvalue matches a desired value, and traces the states of various signalsand components, typically around the time of occurrence of a desiredvalue on bus 155. The manner in which the signals may be generated isdescribed below. Trace system 140 may be implemented in a known way.

[0036] Monitor RAM 120 may be configured by a programmer to specify adesired set of values. Only a small number of memory locations may berequired by using a convention provided in accordance with an aspect ofthe present invention. Monitor circuit 130 and monitor RAM 120 togethermay be referred to as a detection circuit, and operate to compare eachof the present values transmitted on bus 155 with the specified desiredset of values to determine if a match exists. The manner in which such acomparison can be made is described below with reference to exampleembodiment(s).

[0037] 3. Monitor Ram and Monitor Circuit

[0038]FIG. 2 is a block diagram illustrating the details of monitor RAM120 and monitor circuit 130, in one embodiment. Monitor RAM 120 is showncontaining a number of memory locations 220-1 through 220-X, with eachmemory location having a specific address. The address of each memorylocation and the data stored in that memory location together representa desired value (or values) sought to be monitored by a programmer asdescribed below in further detail. The corresponding convention isdescribed first.

[0039] With respect to the convention, each value contains a number ofbits at corresponding bit positions. Assuming an N-bit value, each valuehas bit positions 0 to (N−1). Some of the bit positions are viewed asbeing part of a first set of positions and some other of the bitpositions are viewed as being part of a second set of positions. Forsimplicity it is assumed that the positions in the two sets togethercontain all the N-bits. Thus, the first set may contain bit positions 0through X, and the second set may contain bit positions (X+1) through(N−1).

[0040] Continuing with reference to N-bit values, monitor RAM 120contains memory locations with X-bit addresses. That is, the number ofbits in the address bus of monitor RAM 120 equals the number of bits inthe first set. Each memory location contains the bits of a desired valueat the second set of positions.

[0041] In one embodiment, monitor RAM 120 contains (N−X) bit words. Insuch a situation, the bits of a desired value corresponding to the firstset form the memory address, and the remaining bits are stored in thememory location with the memory address. One problem with such anapproach is that it may not be possible to monitor more than one desiredvalue sharing the same bits in the first set of positions.

[0042] Accordingly, in an alternative embodiment illustrated withreference to FIG. 2, each memory location is shown containing fourcolumns, with each column containing (N−X) bits. Thus, each memorylocation is logically viewed as containing a number of cells equal tothe number of columns (i.e., 4 columns in each location in the presentexample). One bit in each cell is used as a flag. When the flag containsone logical value, the corresponding cell represents a valid desiredvalue and another logical value indicates that the cell does not containvalid desired value. In an embodiment, a flag is implemented as a singlebit.

[0043] Thus, the embodiment of FIG. 2 can be used to specify up to fourdesired values sharing the same bits in the positions corresponding tothe first set. A monitor circuit corresponding to such an approach isdescribed below.

[0044] Monitor circuit 130 is shown containing four comparators 230,240, 250 and 260 corresponding to the four desired values specified byeach memory location of monitor RAM 120. Each comparator compares thebits of a present value in the second set of positions (received on bus155) and the same bit positions of a corresponding desired value storedin monitor RAM 120. Each comparator 230-260 generates one logical value(e.g., 1) if the two inputs match, and another logical value otherwise.

[0045] Thus, the outputs of the comparators can be used to determinewhether a present value matches any of a desired values represented bymonitor RAM 120. The operation of the circuit of FIG. 2 is describedbelow with an example.

[0046] 4. Example

[0047] As an example, it is assumed that the following four values(“desired values”) are to be detected on bus 155, 01010 000011111(“first desired value”), 01001 111110000 (“second desired value”), 01110000101010 (“third desired value”), 01110 010101011 (“fourth desiredvalue”). Each desired value is of 14 bit length and thus contains 14 bitpositions numbered 0-13 for illustration. The bit positions arepartitioned into two sets, the first set containing five bit positions(e.g., positions) 9-13. The second set contain the remaining nine bitpositions, 0-8.

[0048] It should be understood that the bit positions in each of thesets need not be consecutive as in the above illustration. In addition,the number of bits in the first set and the second set need not equalthe total number of bit positions in each value. When such an equalitydoes not exist, the value in each cell represents a range of desiredvalues. Furthermore, some of the less significant bits (i.e., 0-8 in thepresent example) can also be used as an address to monitor RAM 120(instead of the more significant bits 9-13).

[0049] Continuing with the example, the first desired value is assignedto memory location 10 (01010) as the bits together in the first set ofpositions equals 10. The content of the first cell of memory location 10is formed by ten bits, nine of which are set to 000011111 correspondingto the bits (of the first desired value) at the second set of positions.The flag in the tenth bit of the content of the cell is set to 1 toindicate the the cell contains a valid desired value. Similarly, thebits (111110000) in the second set of positions of the second desiredvalue form the content of the cell at memory location 9 (01001).

[0050] The third and fourth desired values are assigned to location 14(01110) as the values share the same value in the first set ofpositions. The contents of the first (corresponding to column left mostcolumn in FIG. 2) and second cells of location 14 may be respectivelyformed by 000101010 and 010101011 representing the bits in the secondset of positions of the third and fourth desired values respectively.The corresponding flags are also set to 1. The flags of all theremaining cells (other than the four for the four desired values) may beset to 0 to indicate that no valid desired value is stored in thecorresponding cells.

[0051] The manner in which a determination can be made as to whether apresent value equals one of the desired values represented by monitorRAM 120 is described now. For illustration, it is assumed that thefollowing three values (“present values”) occur in different bus cycles(or time instances) on bus 155—00011 101010100 (“first present value”),01001 000011111 (“second present value”), 01110 010101011 (“thirdpresent value”). Each bits is of 14 bit word length (same as the lengthof each desired value) and thus contains 14 bit positions numbered 0-13for illustration. The present values are used in conjunction with themonitor RAM 120 and comparators 230, 240, 250 and 260 consistent withthe partitioning approach (i.e., bits 0-8 in the first set of positionsand bits 9-13 in the second set of positions) described above.

[0052] The presence of the first present value (00011 101010100) on bus155 causes the contents of memory location 3 of monitor RAM 120 to beretrieved as the bits together in the first set of positions (of thefirst present value) equals 3 (00011). As the flags of all the fourcells are pre-set to zero (indicating invalid data), all the comparators230, 240, 250 and 260 generate a logical value (e.g., 0) to indicatethat the first present value does not equal any of the desired values.

[0053] The presence of the second present value (01001 000011111) on bus155 causes the contents of memory location 9 of monitor RAM 120 to beretrieved as the bits together in the first set of positions (of thesecond present value) equals 9 (01001). At memory location 9, the flag(ninth bit) in the first cell is pre-set to 1 as the second desiredvalue is represented by the cell. Comparator 230 compares bits in thesecond set of positions of the second present value that is, 000011111,with the content of the first cell with memory location 9 (also000011111), and generates a value of 1 to indicate that a match exists.The remaining comparators 240, 250 and 260 generate an output of 0 asthe flags of the corresponding cells of location 9 are pre-set to 0.

[0054] Similarly, the presence of the third present value (01110010101011) on bus 155 causes the four comparators to compare thecontents of the respective four cells at location 14 with the bits(010101011) at the second set of positions of the third present value.The third and fourth comparators (250 and 260) generate an output of 0as the flag of the corresponding bits is set to indicate that a validpresent value is not represented. Comparator 230 generates an output of0 as the cell contents (000101010) do not match 010101011. However,comparator 240 generates a 1 as the contents of the second cell matchthe bits in the second set of positions of the third present value.

[0055] Thus, the embodiments described above can be used to determinewhether a present value transmitted on a bus equals any one of thedesired values. The determination is performed quickly while using asmall memory unit by using a convention provided in accordance with thepresent invention.

[0056] 5. Conclusion

[0057] While various embodiments of the present invention have beendescribed above, it should be understood that they have been presentedby way of example only, and not limitation. Thus, the breadth and scopeof the present invention should not be limited by any of the abovedescribed exemplary embodiments, but should b e defined only inaccordance with the following claims and their equivalents.

What is claimed is:
 1. A detection circuit for detecting the occurrenceof a one of a plurality of desired values on a bus, said detectioncircuit comprising: a random access memory (RAM) containing a pluralityof locations, each of said plurality of locations being addressed by acorresponding address, storing the bits at a second set of positions ofeach desired value at a location of a random access memory (RAM) havingan address formed by the bits at a first set of positions of the desiredvalue, wherein said first set of positions and said second set ofpositions are non-overlapping; and a comparator comparing an output ofsaid RAM with an another input to generate a result, wherein bits atsaid first set of positions of a present value is provided as an addressto said RAM to cause said RAM to provide the data stored at a locationcorresponding to said address as said output, wherein said location iscomprised in said plurality of locations, wherein bits at said secondset of positions of said present value is provided as said anotherinput, whereby said result indicates whether said present value equalsat least one of said plurality of desired values.
 2. The detectioncircuit of claim 1, wherein each of said plurality of locations containsa plurality of cells, each of said plurality of cells containing anumber of bits equal to the number of positions in said second set ofpositions.
 3. The detection circuit of claim 2, wherein each of saidplurality of cells further comprises a flag indicating whether thecorresponding cell stores a valid desired value.
 4. The detectioncircuit of claim 2, further comprising a plurality of comparators equalin number to the number of said plurality of cells, wherein each of saidplurality of comparators compares a corresponding desired value storedin the corresponding cell, wherein said plurality of comparatorscomprises said comparator.
 5. The detection circuit of claim 1, whereineach of said desired values contain N-bits, wherein N is a positiveinteger, wherein the number of bits in said first set of positions andthe number of bits in said second set of positions equal N.
 6. Thedetection circuit of claim 1, wherein each of said first set ofpositions and said second set of positions are consecutive.
 7. Thedetection circuit of claim 1, wherein at least one of said first set ofpositions and said second set of positions are not consecutive.
 8. Theinvention of claim 5, further comprising a second RAM, wherein said RAMand said second RAM respectively store a first desired value and asecond desired value sharing the same bits in said first set ofpositions.
 9. A system comprising: an addressable unit; processor; a bustransferring a present value between said addressable unit and saidprocessor; a monitor memory containing a plurality of locations, each ofsaid plurality of locations being addressed by a corresponding address,storing the bits at a second set of positions of each desired value at alocation of a random access memory (RAM) having an address formed by thebits at a first set of positions of the desired value, wherein saidfirst set of positions and said second set of positions arenon-overlapping; and a comparator comparing an output of said monitormemory with an another input to generate a result, wherein bits at saidfirst set of positions of said present value is provided as an addressto said monitor memory to cause said monitor memory to provide the datastored at a location corresponding to said address as said output,wherein said location is comprised in said plurality of locations,wherein bits at said second set of positions of said present value isprovided as said another input to said comparator, whereby said resultindicates whether said present value equals at least one of saidplurality of desired values.
 10. The system of claim 9, wherein each ofsaid plurality of locations contains a plurality of cells, each of saidplurality of cells containing a number of bits equal to the number ofpositions in said second set of positions.
 11. The system of claim 10,wherein each of said plurality of cells further comprises a flagindicating whether the corresponding cell stores a valid desired value,said comparator performing a comparison operation only if said flagindicates that the corresponding cell contains a valid desired value.12. The system of claim 10, further comprising a plurality ofcomparators equal in number to the number of said plurality of cells,wherein each of said plurality of comparators compares a correspondingdesired value stored in the corresponding cell, wherein said pluralityof comparators comprises said comparator.
 13. The system of claim 9,wherein the number of bits in said first set and the number of bits insaid second set equal N, wherein each of said desired values containN-bits, wherein N is a positive integer.
 14. The invention of claim 13,wherein said system is implemented in a general purpose computer systemor a real time embedded system, and wherein said addressable data unitcomprises one of a data RAM and a peripheral device.
 15. A detectioncircuit for detecting the occurrence of a one of a plurality of desiredvalues on a bus, each of said desired values containing N-bits, whereinN is a positive integer, said detection circuit comprising: means forstoring the bits at a second set of positions of each desired value at alocation of a random access memory (RAM) having an address formed by thebits of the desired value at a first set of positions; means forproviding as an access address to said RAM, wherein said access addresscomprises the bits of said present value at said first set of positions,wherein said means for providing causes said RAM to generate an output;and means for comparing said output with an another input to generate aresult, wherein said another input comprises the bits of said presentvalue at said second set of positions, wherein said result indicateswhether said present value matches one of said plurality of desiredvalues.
 16. The detection circuit of claim 15, wherein each of saidplurality of locations contains a plurality of cells, each of saidplurality of cells containing a number of bits equal to the number ofpositions in said second set of positions.
 17. The detection circuit ofclaim 16, wherein each of said plurality of cells further comprises ameans for indicating whether the corresponding cell stores a validdesired value.
 18. The detection circuit of claim 16, further comprisinga plurality of means for comparing equal in number to the number of saidplurality of cells, wherein each of said plurality of means forcomparing compares a corresponding desired value stored in thecorresponding cell, wherein said plurality of means for comparingcomprises said means for comparing.
 19. A method of determining whethera present value matches one of a plurality of desired values, saidmethod comprising: storing the bits at a second set of positions of eachdesired value at a location of a random access memory (RAM) having anaddress formed by the bits of the desired value at a first set ofpositions; providing an access address to said RAM, wherein said accessaddress comprises the bits of said present value at said first set ofpositions, wherein said providing causes said RAM to generate an output;and comparing said output with an another input to generate a result,wherein said another input comprises the bits of said present value atsaid second set of positions, wherein said result indicates whether saidpresent value matches one of said plurality of desired values.
 20. Themethod of claim 19, wherein said location contains a plurality of cells,each of said plurality of cells containing a number of bits equal to thenumber of positions in said second set of positions, said method furthercomprising storing bits at said second set of positions of a firstdesired value in a first cell and storing bits at said second set ofpositions of a second desired value in a second cell, wherein said firstdesired value and said second desired value are comprised in saidplurality of values and wherein said first cell and said second cell arecomprised in said plurality of cells.
 21. The method of claim 20,further comprising including a flag in each of said plurality of cells,wherein said flag indicates whether a valid desired value is stored in acorresponding one of said plurality of cells.
 22. The method of claim20, further comprising comparing the bits of said present value in saidsecond set of positions with the content of each of said plurality ofcells contained in a location corresponding to said access address.